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賀！“Efficient and Effective Macro Placement for Very Large Scale Designs Using RL and MCTS Integration” accepted in DATE 2024. (Author: J.-M. Lin, Z.-Z. Lee, N.-C. Lin)
賀！“An Effective Analytical Placement Approach to Handle Fence Region Constraint” accepted in ICCAD 2024. (Author: J.-M. Lin, Y.-C. Chen, W.-Y. Lin, P.-Y. Chen)
賀！張瑋倫、趙品倫、蘇秉逸同學榮獲《2024積體電路電腦輔助設計軟體製作競賽》佳作
賀！林維淵、黃昱東、李宗澤、謝翔宇同學榮獲《2023積體電路電腦輔助設計軟體製作競賽》佳作
賀！林均致、黃兆賢、朱恩翔同學榮獲《2023積體電路電腦輔助設計軟體製作競賽》佳作
賀！林妤蒨同學榮獲《中國電機工程師學會青年論文獎》第二名
賀！“Timing-Driven Analytical Placement According to Expected Cell Distribution Range” accepted in ISPD 2024. (Author: J.-M. Lin, Y.-Y. Chang, W.-L. Huang)
賀！“HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique” accepted in ICCAD 2023. (Author: J.-M. Lin, Y.-C. Lin, H. Kung and W.-Y. Lin)
賀！“Routablity-driven Orienation-aware Analytical Placement for System in Package” accepted in ICCAD 2023. (Author: J.-M. Lin, T.-C. Tsai and R.-T. Shen)
賀！“Voltage-Drop Optimization Through Insertion of Extra Stripes To A Power Delivery Network” accepted in ISPD 2023. (Author: J.-M. Lin, Y.-T. Chen, Y.-T. Kung and H.-J. Lin)
賀！呂柏辰同學榮獲《中國電機工程師學會青年論文獎》佳作
賀！沈睿霆、莊文瑞同學榮獲《2022積體電路電腦輔助設計軟體製作競賽》優等
賀！“PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability” accepted in IEEE TVLSI 2022. (Author: J.-M. Lin, L.-C. Zane, M.-C. Tsai, Y.-C. Chen, C.-L. Lin and C.-F. Tsai)
賀！林家民教授榮獲《中國工程師學會高雄分會工程教授獎》
賀！林家民教授榮獲《中國電機工程師學會傑出電機工程教授獎》
賀！“A Novel Blockage-avoiding Macro Placement Approach for 3D ICs based on POCS” accepted in ICCAD 2022. (Author: J.-M. Lin, P.-C. Lu, H.-Y. Lin and J.-T. Tsai)
賀！“Routability-driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs” accepted in ICCAD 2022. (Author: J.-M. Lin, H.-Y. Hsieh, H. Kung and H.-J. Lin)
賀！黃瑋凡同學榮獲《中國電機工程師學會青年論文獎》第三名
賀！沈睿霆、王柏智同學榮獲《2021積體電路電腦輔助設計軟體製作競賽》優等
賀！“Thermal-aware Floorplanning and TSV-planning for Mixed-Type Modules in a Fixed-outline 3D IC” accepted in TVLSI 2021. (Author: J.-M. Lin, W.-Y. Chang, H.-Y. Hsieh , Y.-T. Shyu , Y.-J. Chang)
賀！“Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs” accepted in ICCAD 2021. (Author: Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Chen-Fa Tsai and Che-Li Lin)
賀！“A Dataflow-aware Analytical Placement Algorithm for Modern Mixed-size Circuit Designs” accepted in ICCAD 2021. (Author: Jai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang and Po-Wen Wang)
賀！“Thermal-aware Fixed-outline Floorplanning Using Analytical Models with Thermal-Force Modulation” accepted in TVLSI 2021. (Author: J.-M. Lin, T.-T. Chen, H.-Y. Hsieh, Y.-T. Shyu, Y.-J. Chang, and J.-M. Lu)
賀！“Dataflow-aware Macro Placement based on Simulated Evolution Algorithm for Mixed-Size Designs” accepted in TVLSI 2021. (Author: J.-M. Lin, Y.-L. Deng, Y.-C. Yang, and J.-J. Chen, P.-C. Lu)
賀！“A Fast PowerNetwork Optimization Algorithm for Improving Dynamic IR-Drop” accepted in ISPD 2021. (Author: J.-M. Lin, Y.-T. Kung, Z.-Y. Huang and I.-R. Chen)
賀！“A Novel Macro Placement Approach based on Simulated Evolution Algorithm” accepted in ICCAD 2019. (Author: J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and Y.-C. Chen)
賀！“Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros” accepted in DAC 2019. (Author: J.-M. Lin, S.-T. Li and Y.-T. Wang)
賀！“Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits with Obstacles” accepted in TVLSI 2018. (Author: J.-M. Lin, Y.-L. Deng, S.-T. Li, B.-H. Yu, L.-Y. Chang and T.-W. Peng)
賀！“A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models” accepted in ICCAD 2018. (Author: J.-M. Lin, T.-T. Chen, Y.-F. Chang, W.-Y. Chang, Y.-T. Shyu, Y.-J. Chang and J.-M. Lu)
賀！“Macro-Aware Row-Style Power Delivery Network Design for Better Routability” accepted in ICCAD 2018. (Author: J.-M. Lin, J.-S. Syu and I.-R. Chen)
賀！“General Floorplanning Methodology for 3D ICs with an Arbitrary Bonding Style” accepted in DATE 2018. (Author: J.-M. Lin and C.-Y. Huang)
賀！“Co-Synthesis of Floorplanning and Powerplanning in 3D ICs for Multiple Supply Voltage Designs” accepted in DATE 2018. (Author: J.-M. Lin, C.-Y. Huang and J.-Y. Yang)
賀！陳泰廷、鄧有倫、王奕文同學榮獲《2017國際積體電路電腦輔助設計軟體製作競賽－國際賽定題組C題》榮譽提名
賀！“Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs” accepted in TCAD 2017. (Author: J.-M. Lin and J.-A. Yang)
賀！“Regularity-Aware Routability-Driven Placement Prototyping Algorithm for Hierarchical Mixed-Size Circuits” accepted in ASP-DAC 2017. (Author: J.-M. Lin, B.-H. Yu and L.-Y. Chang)
賀！“SAINT: Handling Module Folding and Alignment in Fixed-Outline Floorplans for 3D ICs” accepted in ICCAD 2016. (Author: J.-M. Lin, B.-Y. Chiu and Y.-F. Chang)
賀！“An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs” accepted in TCAD 2016. (Author: Y.-T. Shyu, J.-M. Lin, C.-C. Lin, C.-P. Huang and S.-J. Chang)
賀！“A Systematic Design Methodology of Asynchronous SAR ADCs” accepted in TVLSI 2015. (Author: C.-P. Huang, J.-M. Lin , Y.-T. Shyu and S.-J. Chang)
賀！“Placement Density Aware Power Switch Planning Methodology for Power Gating Design” accepted in TCAD 2015. (Author: J.-M. Lin and C.-C. Lin)
賀！“Routability-Driven Floorplanning Algorithm for Mixed-Size Modules with Fixed-Outline Constraint” accepted in VLSI-DAT 2015. (Author: J.-M. Lin, C.-Y. Hu and K.-C. Chan)
賀！王郁仁、李宗霖、蔡榮陽同學榮獲《2013國際積體電路電腦輔助設計軟體製作競賽－平台開發組》佳作
賀！詹凱仲、吳季恒、林哲均、吳佩珊同學榮獲《2012國際積體電路電腦輔助設計軟體製作競賽－定題組》優等
賀！李宗霖同學榮獲《2012國際積體電路電腦輔助設計軟體製作競賽－平台開發組》佳作

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