• 期刊論文 Journal Papers
• J.-M. Lin, L.-C. Zane, M.-C. Tsai, Y.-C. Chen, C.-L. Lin and C.-F. Tsai, “PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 30, No. 11, pp. 1783-1793, Sept. 2022.
• J.-M. Lin, W.-Y. Chang, H.-Y. Hsieh , Y.-T. Shyu , Y.-J. Chang, “Thermal-aware Floorplanning and TSV-planning for Mixed-Type Modules in a Fixed-outline 3D IC ”in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, No. 9, pp. 1652-1664, Sept. 2021.
• J.-M. Lin, T.-T. Chen, H.-Y. Hsieh, Y.-T. Shyu, Y.-J. Chang, and J.-M. Lu, “Thermal-aware Fixed-outline Floorplanning Using Analytical Models with Thermal-Force Modulation, ” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, No. 5, pp. 985-997, May. 2021.
• J.-M. Lin, Y.-L. Deng, Y.-C. Yang, and J.-J. Chen, P.-C. Lu, “Dataflow-aware Macro Placement based on Simulated Evolution Algorithm for Mixed-Size Designs,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, No. 5, pp. 973-984, May. 2021.
• J.-M. Lin, Y.-L. Deng, S.-T. Li, B.-H. Yu, L.-Y. Chang and T.-W. Peng, “Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits with Obstacles,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 27, No. 1, pp. 57-68, Jan. 2019.
• J.-M. Lin and J.-A. Yang, “Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No. 11, pp. 1856-1868, Nov. 2017.
• Y.-T. Shyu, J.-M. Lin, C.-C. Lin, C.-P. Huang and S.-J. Chang, “An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 10, pp. 1730-1743, Oct. 2016.
• C.-P. Huang, J.-M. Lin, Y.-T. Shyu and S.-J. Chang, “A Systematic Design Methodology of Asynchronous SAR ADCs,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 23, No. 99, pp. 1-14, Nov. 2015.
• J.-M. Lin and C.-C. Lin, “Placement Density Aware Power Switch Planning Methodology for Power Gating Design,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No. 5, pp. 766-777, May 2015.
• J.-M. Lin and J.-H. Wu, “F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 11, pp. 1681-1692, Nov. 2014.
• Y.-T. Shyu, J.-M. Lin, C.-P. Huang, C.-W. Lin, Y.-Z. Lin and S.-J. Chang, “Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No 4, pp. 624-635, Apr. 2013.
• C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang and S.-J. Chang, “Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 12, pp. 1789-1802, Dec. 2012.
• J.-M. Lin and Z.-X. Hung, “SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 20, No. 3, pp. 473-484, Mar. 2012.
• J.-M. Lin and Z.-X. Hung, “UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 7, pp. 1034-1044, Jul. 2011.
• J.-M. Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 13, No. 2, pp. 288-292, Feb. 2005.
• J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-Admissible Representations for General Floorplans,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 6, pp. 968-980, Jun. 2004.
• J.-M. Lin, S.-P. Lin and Y.-W. Chang, “Corner Sequence: A P-Admissible Floorplan Representation with a Worst-Case Linear-Time Packing Scheme,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 11, No. 4, pp. 679-686, Aug. 2003.
• J.-M. Lin, H.-L. Chen and Y.-W. Chang, “Arbitrarily Shaped Rectilinear Module Placement Using TCG,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 10, No. 6, pp. 886-901, Dec. 2002.
• G.-M. Wu, J.-M. Lin and Y.-W. Chang, “Performance-Driven Placement for Dynamically Reconfigurable FPGAs,” in ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 4, pp. 628-642, Oct. 2002.
• J.-M. Lin, H.-E. Yi and Y.-W. Chang, “Module Placement with Boundary Constraints Using B*-Trees,” in IEE Proceedings - Circuits, Devices and Systems (EI/SCI), Vol. 149, No. 4, pp. 251-256, Aug. 2002.
• G.-M. Wu, J.-M. Lin and Y.-W. Chang, “Generic ILP-Based Approaches for Time-Multiplexed FPGA Partitioning,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 10, pp. 1266-1274, Oct. 2001.
• Y.-W. Chang, J.-M. Lin and D. F. Wong, “Matching-Based Algorithm for FPGA Channel Segmentation Design,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 6, pp. 784-791, Jun. 2001.
• 國際會議論文 International Conference Papers
• J.-M. Lin, Z.-Z. Lee, N.-C. Lin “Efficient and Effective Macro Placement for Very Large Scale Designs Using RL and MCTS Integration” in Proc. of IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE),2025.
• J.-M. Lin, Y.-C. Chen, W.-Y. Lin, P.-Y. Chen “An Effective Analytical Placement Approach to Handle Fence Region Constraint” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2024.
• J.-M. Lin, Y.-Y. Chang and W.-L. Huang “Timing-Driven Analytical Placement According to Expected Cell Distribution Range” in Proc. of ACM International Symposium on Physical Design (ISPD),2024.
• J.-M. Lin, Y.-C. Lin, H. Kung and W.-Y. Lin “HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2023.
• J.-M. Lin, T.-C. Tsai and R-T. Shen “Routablity-driven Orienation-aware Analytical Placement for System in Package” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2023.
• J.-M. Lin, Y.-T. Chen, Y.-T. Kung and H.-J. Lin “Voltage-Drop Optimization Through Insertion of Extra Stripes To A Power Delivery Network” in Proc. of ACM International Symposium on Physical Design (ISPD), Virtual Event, U.S.A., pp. 35-43, Mar. 2023.
• J.-M. Lin, P.-C. Lu, H.-Y. Lin and J.-T. Tsai “A Novel Blockage-avoiding Macro Placement Approach for 3D ICs based on POCS,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, U.S.A., pp. 1-7, Mar. 2022.
• J.-M. Lin, H.-Y. Hsieh, H. Kung and H.-J. Lin “Routability-driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, U.S.A., pp. 1-8, Mar. 2022.
• J.-M. Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Chen-Fa Tsai and Che-Li Lin, “Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), New Orleans, LA U.S.A., pp. 1-8, Nov. 2021.
• J.-M. Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang and Po-Wen Wang, “A Dataflow-aware Analytical Placement Algorithm for Modern Mixed-size Circuit Designs,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), New Orleans, LA U.S.A., pp.1-8, Nov. 2021.
• J.-M. Lin, Y.-T. Kung, Z.-Y. Huang and I.-R. Chen, “A Fast Power Network Optimization Algorithm for Improving Dynamic IR-Drop,” in Proc. of ACM International Symposium on Physical Design (ISPD), Virtual Event, U.S., pp. 91-98, Mar. 2021.
• J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and Y.-C. Chen, “A Novel Macro Placement Approach based on Simulated Evolution Algorithm,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1-7, Nov. 2019.
• J.-M. Lin, S.-T. Li and Y.-T. Wang, “Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros,” in Proc. of IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV U.S.A., pp. 1-6, June. 2019.
• J.-M. Lin, T.-T. Chen, Y.-F. Chang, W.-Y. Chang, Y.-T. Shyu, Y.-J. Chang and J.-M. Lu, “A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, CA U.S.A., pp. 1-8, Nov. 2018.
• J.-M. Lin, J.-S. Syu and I.-R. Chen, “Macro-Aware Row-Style Power Delivery Network Design for Better Routability,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, CA U.S., pp. 1-8, Nov. 2018.
• J.-M. Lin and C.-Y. Huang, “General Floorplanning Methodology for 3D ICs with an Arbitrary Bonding Style,” in Proc. of IEEE/ACM Design Automation and Test in Europe Conference and Exhibition (DATE), pp. 1199-1202, Mar. 2018.
• J.-M. Lin, C.-Y. Huang and J.-Y. Yang, “Co-Synthesis of Floorplanning and Powerplanning in 3D ICs for Multiple Supply Voltage Designs,” in Proc. of IEEE/ACM Design Automation and Test in Europe Conference and Exhibition (DATE), pp. 1339-1344, Mar. 2018.
• J.-M. Lin, B.-H. Yu and L.-Y. Chang, “Regularity-Aware Routability-Driven Placement Prototyping Algorithm for Hierarchical Mixed-Size Circuits,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, pp. 438-443, Jan. 2017.
• J.-M. Lin, B.-Y. Chiu and Y.-F. Chang, “SAINT: Handling Module Folding and Alignment in Fixed-Outline Floorplans for 3D ICs,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1-7, 2016.
• J.-M. Lin, C.-C. Lin, Z.-W. Syu, C.-C. Tsai and K. Huang, “Current Density Aware Power Switch Placement Algorithm for Power Gating Designs,” in Proc. of ACM International Symposium on Physical Design (ISPD), Petaluma, CA U.S.A., pp. 85-92, Mar. 2014.
• K.-C. Chan, J.-M. Lin and C.-J. Hsu, “A Flexible Fixed-Outline Floorplanning Methodology for Mixed-Size Modules,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 435-440, Jan. 2013.
• C.-W. Lin, C.-L. Lee, J.-M. Lin and S.-J. Chang, “Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA U.S.A., pp. 635-642, Nov. 2012.
• C.-W. Lin, C.-C. Lu, J.-M. Lin and S.-J. Chang, “Routability-Driven Placement Algorithm for Analog Integrated Circuits,” in Proc. of ACM International Symposium on Physical Design (ISPD), Napa, CA U.S.A., pp. 71-78, Mar. 2012.
• J.-M. Lin, W.-Y. Cheng, C.-L. Lee and C.-J. Hsu, “Voltage Island-Driven Floorplanning Considering Level Shifter Placement,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, pp. 443-448, Feb. 2012.
• C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang and S.-J. Chang, “Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits,” in Proc. of ACM/IEEE Design Automation Conference (DAC), San Diego, CA U.S.A., pp. 528-533, Jun. 2011.
• C.-W. Lin, C.-C. Lu, C.-P. Huang, S.-J. Chang and J.-M. Lin, “Routing Aware Placement Algorithms for Modern Analog Integrated Circuits,” in Proc. of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, pp. 1-4, Aug. 2011.
• J.-M. Lin and J.-R. Chuang, “Efficient Multi-Layer Obstacle-Avoiding Preferred Direction Rectilinear Steiner Tree Construction,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 527-532, Jan. 2011.
• C.-W. Lin, J.-M. Lin, C.-P. Huang and S.-J. Chang, “Performance-Driven Analog Placement Considering Boundary Constraint,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Anaheim, CA U.S.A, pp. 292-297, Jun. 2010.
• J.-M. Lin and H. Hung, “UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, pp. 555-560, Jan. 2010.
• J.-M. Lin, G.-M. Wu, Y.-W. Chang and R.-H. Chuang, “Module Placement with the Symmetry Constraint for Analog Design Using TCG-S,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 1135-1138, Jan. 2004.
• J.-M. Lin, S.-R. Pan and Y.-W. Chang, “Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing,” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, pp. 851-854, Jan. 2003.
• J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-Admissible Representations for General Floorplans,” in Proc. of ACM/IEEE Design Automation Conference (DAC), New Orleans, LA U.S.A., pp. 842-847, Jun. 2002.
• J.-M. Lin, H.-L. Chen and Y.-W. Chang, “Arbitrary Convex and Concave Rectilinear Module Packing Using TCG,” in Proc. of IEEE/ACM Design Automation and Test in Europe Conference (DATE), Paris, France, pp. 69-75, Mar. 2002.
• J.-M. Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV U.S.A., pp. 764-769, Jun. 2001.
• G.-M. Wu, J.-M. Lin, C.-T. M. Chao and Y.-W. Chang, “Generic ILP-Based Approaches for Time-Multiplexed FPGA Partitioning,” in Proc. of IEEE International Conference on Computer Design (ICCD), Austin, TX U.S.A., pp. 764-769, Sep. 2001.
• G.-M. Wu, J.-M. Lin and Y.-W. Chang, “An Algorithm for Dynamically Reconfigurable FPGAs Placement,” in Proc. of IEEE International Conference on Computer Design (ICCD), Austin, TX U.S.A, pp. 501-504, Sep. 2001.
• Y.-W. Chang, J.-M. Lin and D. F. Wong, “Graph Matching-Based Algorithms for FPGA Segmentation Design,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, CA U.S.A., pp. 34-39, Nov. 1998.
• 國內會議論文 National Conference Papers
• J.-M. Lin, C.-Y. Hu and K.-C. Chan, “Routability-Driven Floorplanning Algorithm for Mixed-Size Modules with Fixed-Outline Constraint,” in Proc. of IEEE VLSI Design, Automation and Text (VLSI-DAT), Hsinchu, Taiwan, pp. 1-4, Apr. 2015.
• Y.-F. Hsiao, C.-C. Tsai, C.-C. Huang, J.-M. Lin and C.-C. Lin, “Signal Routing of Power Switches for Low Power Designs,” in Proc. of the 24th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2013.
• C.-W. Lin, Y.-C. Chiu, C.-P. Huang, S.-J. Chang and J.-M. Lin, "Mismatches-Aware Common-Centroid Placement for Capacitor Arrays," in Proc. of the 22th VLSI Design/CAD Symposium, Yunlin, Taiwan, 2011.
• J.-M. Lin and S.-A. Hwang, “Diffusion-Based Approach for Global Placement,” in Proc. of the 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.
• J.-M. Lin, S.-P. Lin and Y.-W. Chang, “A P-Admissible Non-Slicing Floorplan Representation with a Worst-Case Linear-Time Packing Scheme,” in Proc. of The 12th VLSI Design/CAD Symposium, Taiwan, Hsinchu, Aug. 2001.
• J.-M. Lin, S.-R. Pan and Y.-W. Chang, “A Timing-Driven Matching-Based Algorithm for Array-Based FPGA Routing,” in Proc. of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1999.